The high performance of FPGA (Field Programmable Gate Array) in image processing\napplications is justified by its flexible reconfigurability, its inherent parallel nature and the availability\nof a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been\nfound to be significantly advantageous in certain application domains including image processing\nbecause of its lower hardware complexity and power consumption. However, its viability is deemed\nto be limited due to its serial bitstream processing and excessive run-time requirement for convergence.\nTo address these issues, a novel approach is proposed in this work where an energy-efficient\nimplementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number\nGenerators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage\nFPGA�s reconfigurability and abundant internal memory resources. the proposed approach has\nbeen tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel\nimplementations of conventional stochastic computation using the well-known SC edge detection\nand multiplication circuits. Results prove that by using this approach, execution time, as well\nas the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit\nand multiplication circuit, respectively.
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